3 接口电路的实现 Verilog HDL 3描述硬件单元的结构简单且易读,是当前最流行和通用的两种硬件描述语言之一,得到众多EDA工具的支持,因此利用该语言进行电路设计可以节省开发成本并缩短开发周期。
3.1 接口电路的顶层Verilog HDL描述 module DSP_TLC(SCLK1, DX1, FSX1, EODX1, DR1, FSR1, EODR1,SCLK0, DX0, FSX0, EODX0, DR0, FSR0, EODR0, CLKX, DX, FSX, DR, FSR, RESET); input FSX1, EODX1, FSX0, EODX0, DX, CLKX, RESET; output FSX, DX1, DX0 input DR1, SCLK1, FSR1, EODR1, DR0, SCLK0, FSR0, EODR0; output FSR, DR Transmit TRA(DX1, SCLK1, FSX1, EODX1, DX0, SCLK0, FSX0, EODX0, DX, CLKX, FSX, RESET); Receive REC(DR1, SCLK1, FSR1, EODR1, DR0, SCLK0, FSR0, EODR0, DR, CLKX, FSR, RESET); endmodule 3.2 发送接口电路的Verilog HDL描述 module Transmit(DX1, SCLK1, FSX1, EODX1, DX0, SCLK0,FSX0, EODX0, DX, CLKX, FSX, RESET); input SCLK1, FSX1, EODX1, SCLK0, FSX0, EODX0; input DX, CLKX, RESET output FSX, DX1, DX0; reg [31:0] tmp_DX, temp_DX; reg [1:0] tmp_EODX; reg [4:0] DX_count; assign DX1 = temp_DX[31]; assign DX0 = temp_DX[15] assign FSX = (tmp_EODX == 2'b11) ? 1'b0 : 1'b1; always @(negedge CLKX or negedge RESET) begin if (RESET == 1′b0) begin tmp_DX <= 32'b0 tmp_EODX <= 2'b0 DX_count <= 5'b0 end else begin if (EODX1 == 1'b0) tmp_EODX[1] <= 1'b1; if (EODX0 == 1'b0) tmp_EODX[0] <= 1'b1 if (DX_count == 5'b11111) tmp_EODX <= 2'b0 if (FSX == 1'b0) begin tmp_DX[0] <= DX tmp_DX[31:1] <= tmp_dx[30:0] DX_count <= DX_count + 1 end else DX_count <= 5'b0 end end always @(posedge SCLK1) begin if (FSX1 == 1'b0) temp_DX[31:17] <= temp_DX[30:16] else temp_DX[31:16] <= tmp_DX[31:16] end always @(posedge SCLK0) begin if (FSX0 == 1'b0) temp_DX[15:1] <= temp_DX[14:0]; else temp_DX[15:0] <= tmp_DX[15:0] end endmodule 3.3 接收接口电路的Verilog HDL描述 module Receive(DR1, SCLK1, FSR1, EODR1, DR0, SCLK0, FSR0, EODR0, DR, CLKR, FSR, RESET); input DR1, SCLK1, FSR1, EODR1, DR0, SCLK0, FSR0, EODR0; input CLKR, RESET; output FSR, DR; reg [31:0] tmp_DR, temp_DR; reg [1:0] tmp_EODR; reg [4:0] DR_count; assign DR = (FSR == 1'b0) ? tmp_DR[31] : 1'bz; assign FSR = (tmp_EODR == 2'b11) ? 1'b0 : 1'b1; always @(posedge CLKR or negedge RESET) begin if (RESET == 1'b0) begin tmp_DR <= 32'b0; tmp_EODR <= 2'b0; DR_count <= 5'b0; end else begin if (EODR1 == 1'b0) tmp_EODR[1] <= 1'b1; if (EODR0 == 1'b0) tmp_EODR[0] <= 1'b1; if (DR_count == 5'b11111) tmp_EODR <= 2'b0; if (FSR == 1'b0) begin tmp_DR[31:1] <= tmp_DR[30:0] DR_count <= DR_count + 1; end else begin DR_count <= 5'b0; Tmp_DR <= temp_DR; end end end always @(negedge SCLK1) begin if (FSR1 == 1'b0) begin temp_DR[16] <= DR1 temp_DR[31:17] <= temp_DR[30:16]; end end always @(negedge SCLK0) begin if (FSR0 == 1'b0) begin temp_DR[0] <= DR0; temp_DR[15:1] <= temp_DR[14:0]; end end endmodule 本文介绍了一种TMS320C3X串口扩展技术,并用Verilog HDL语言进行了描述,利用中小容量的CPLD或FPGA就能实现该接口功能。该电路已被作者应用到实际系统中,仿真和实践证明该接口稳定可靠,具有一定的应用价值。
|